Dr. Bilal Zafar

Bilal Zafar recently joined the University of Central Punjab as Associate Professor in the Department of Electrical Engineering. Before joining UCP, Dr. Zafar was worked at California-based Qualcomm Inc. as Principal Engineer, co-leading a global Custom and Semi-Custom Circuit Implementation team. His team was focused on end-to-end delivery (from RTL to GDSII) of custom IP blocks like on-chip cache memories, FIFOs, and latch arrays to a wide array of Qualcomm products in 28nm through 7nm process technology nodes.

Prior to joining Qualcomm, Dr. Zafar was an adjunct faculty member at the University of Southern California, Los Angeles where he taught Computer Architecture. He worked as Postdoctoral Research Assistant at the Information Sciences Institute working on Exascale Computing project.

Dr. Zafar holds a PhD and MSc in Computer Engineering from the Viterbi School of Engineering at the University of Southern California, Los Angeles, and B.Sc. in Electronics Engineering from Ghulam Ishaq Khan Institute of Engineering Sciences and Technology, Topi. His research interests include heterogeneous architectures, low power circuit design and network-on-chip.

  • Microcontroller-Based Design
  • Digital Logic Design

Education

PhD in Computer Engineering
University of Southern California

MSc in Computer Engineering
University of Southern California

BSc in Electronics Engineering
GIK Institute of Engineering Sciences and Technology

Experience

Q u a l c o m m I n c . , S a n D i e g o C A
Principal Engineer/Manager, Custom and Semi-Custom Implementation Team
  • Co-led Custom & Semi-Custom Implementation (CSI) team – a vertically integrated ASIC design team with expertise in RTL design, synthesis, place & route, custom circuits and physical layout & verification. CSI team has delivered RTL2GDSII views for dozens of complex IPs, including cache memories, FIFOs, sensors, clock dividers, in four process technology nodes (28nm, 14nm, 10nm and 7nm), multiple foundries (TSMC, Global Foundries and Samsung) and over 12 SoC products.
  • Led the design & development of Cache Logical Bank, part of Qualcomm’s first System Cache
    implemented in Snapdragon 845.
  • Initiated and managed R&D Initiatives Central Engineering & Technology (CET) organization to reduce Average Unit Cost (AuC) of Qualcomm products by approx. $76 million in FY`17.
  • Co-led the development of an in-house design and analysis flow (Qdflow) for speedy
    development, verification and release of custom hard-macros. This flow is currently being used for development of 100s of complex IPs across Qualcomm teams.
  • Developed Scannable Small Memories architecture to reduce Design-for-Test overhead for <16KB
    on-chip SRAMs.
  • Managed resources, schedules and secured funding for projects from other Business Units for world-wide team (San Diego, Austin and Bangalore). Responsible for hiring, performance reviews budgets projections, and design reviews.
  • Tools: Verilog RTL; Synopsys Suite – Design Compiler, IC Compiler II, StarRC, PrimeTime, HSPICE; Cadence Suite – Genus, Conformal LEC, First Encounter, Innovus, Virtuoso; Mentor Graphics Modelsim and Tessent MemoryBIST.
U n i v e r s i t y o f S o u t h e r n C a l i f o r n i a , L o s A n g e l e s , C A
Lecturer (Part-Time), Ming Hsieh Department of Electrical Engineering
  • Instructor for EE 352L: Computer Organization and Architecture. This undergraduate class for students in the top-ranked Computer Science (Games) program, covers topics including: Basic CMOS Design; MIPS assembly programming; Pipelined CPU design; Instruction- and Thread-level Parallelism; NVIDIA CUDA architecture and programming; Storage and Interconnection network sub-systems.
I n f o r m a t i o n S c i e n c e s I n s t i t u t e , U S C , M a r i n a d e l R e y , C A
Research Assistant, Computational Sciences Group
  • As part of a multi-university team, we evaluated enabling technologies, micro-architectures, and hardware system design for an Exascale point design study. Collaborators included Louisiana State University, University of Illinois (UIUC), and Sandia National Laboratory.
  • As member of the MulitScale System Center, a Focused Research Center funded by the Semiconductor Research Corporation, I analyzed communication behavior of parallel applications to identify opportunities for dynamic reconfiguration and run-time power management.
I n t e l C o r p , M i c r o p r o c e s s o r R e s e a r c h L a b , S a n t a C l a r a , C A
Graduate Intern, Platform Architecture Research
  • Developed analytical models to prune the design space of on-chip network topologies for power and performance. Developed simulation models using SAS/Workbench for various hierarchical ring-based topologies and compared their performance against mesh topologies of various sizes.
U n i v e r s i t y o f S o u t h e r n C a l i f o r n i a , L o s A n g e l e s , C A
Teaching Assistant, Ming Hsieh Department of Electrical Engineering
  • As TA for EE 560, a graduate-level digital design class, I designed and supervised FPGA-based projects (pipelined CPU & router design) and led discussion sessions on topics including Verilog HDL, FPGA architecture and synthesis, static timing analysis, wave pipelining, slack borrowing and FIFO design.
  • As the head TA for EE 201L, an introductory digital design laboratory, I co-authored the lab manual, and designed multiple new lab exercises. In addition, I was responsible for conducting weekly lab sessions, supervising FPGA-based design projects and mentoring teaching assistance.

List of Publications

Research Publications
  1. Bilal Zafar, Jeff Draper, and Timothy Mark Pinkston. “Cubic Ring Network: A Polymorphic Topology for On-Chip Networks”, In ICPP ‘10: Proceedings of the 39th International Conference on Parallel Processing. San Diego, CA. September, 2010.
  2. Bilal Zafar, Timothy Mark Pinkston, Aurelio Bermúdez, and José Duato. “Deadlock-free Dynamic Reconfiguration Over InfiniBand™ Networks”, Journal of Parallel Algorithms and Applications 19 (2-3):127-143 (2004).
  3. D. N. Jayasimha, Bilal Zafar, and Yatin Hoskote, “On-Chip Interconnection Networks: Why They are Different and How to Compare Them”, Technology Report, Intel Corp., http://blogs.intel.com/research/terascale/ODI why-different.pdf
  4. Timothy Mark Pinkston, Bilal Zafar, and José Duato, “A Method for Applying Double Scheme Dynamic Reconfiguration over InfiniBand™”, In PDPTA ’03: International Conference on Parallel and Distributed Processing Techniques and Applications, June 2003.
  5. Bilal Zafar and Jeff Draper. “Polymorphic Networks-On-Chip for Dynamic Power Management And Fault Tolerance.” Doctoral Showcase, In SC’10: 23rd ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis. New Orleans, LA. November, 2010.
  6. Bilal Zafar and Jeff Draper. “Cubic Ring: A Polymorphic NoC for Dynamic Power Reduction and Fault Tolerance.” Poster, Multiscales Center (MuSyC) Joint Review, San Jose, CA, September, 2010. http://www.musyc.org/pubs/123.html
  7. Bilal Zafar. “Hardware Designs / Components for Exascale Systems: Technology Projections.” Presentation, NSF Exascale Point Design Study, Center for Computing and Technology, Louisiana State University, Baton Rouge, LA, March 19-20, 2009

Patents

  1. Hari Rao, Venkatasubramanian Narayanan, Venugopal Boynapalli, Sagar Suresh Sabade, Bilal Zafar,
    Buffer testing for reconfigurable instruction cell arrays. U.S. Patent US-9081060-B2, filed October 4,
    2013, and issued July 14, 2015.
  2. Venugopal Boynapalli, Bilal Zafar, Shared repair register for memory redundancy. U.S. Patent US-
    9230691-B1, filed November 6, 2014, and issued January 5, 2016.
  3. Lipeng Cao, Dorav Kumar, Bilal Zafar, Ramaprasath Vilangudipitchai, Venkatasubramanian
    Narayanan, Xi Luo, Adjustable power rail multiplexing, U.S. Patent US-9852859-B2, filed December 28,
    2015, and issued December 26, 2017.
  4. Venugopal Boynapalli, Kashyap Ramachandra Bellur, Prabaharan Balu, Bilal Zafar, Alex Dongkyu Park, Sei Seung Yoon, Scannable memories with robust clocking methodology to prevent inadvertent reads or writes, U.S. Patent Application US-2016078965-A1, filed September 16, 2014, Issued May 30, 2015.
  5. Bilal Zafar, Rakesh Vattikonda, De Lu, Venkatasubramanian Narayanan, Masoud Zamani, Joseph Fang, Apparatus and method for employing mutually exclusive write and read clock signals in scan capture mode for testing digital, U.S. Patent Application US-2018074126-A1, filed September 12, 2016.
  6. Masoud Zamani, Bilal Zafar, Venkatasubramanian Narayanan, Apparatus and method of clock shaping for memory, U.S. Patent Application US-10163474B2, filed September 22, 2016, Issued Dec 25, 2018.
  7. Dorav Kumar, Venkat Narayanan, Bilal Zafar, Seid Hadi Rasouli, Venugopal Boynapalli, Pulse-stretcher clock generator circuit for high speed memory subsystems, U.S Patent Application US- US20180158506A1, filed December 6, 2016, Issued June 5, 2018.

Honors

Best Teaching Assistant for Undergraduate Class, 2007
Ming Hsieh Department of Electrical Engineering, USC

Teaching Assistants Fellow, 2006-08
Selected as one of only two TAs from the School of Engineering, helped develop an on-line resource for teaching assistants and language instructors university-wide (available at: uscta.wikidot.com), and served as a panelists (twice) during the university-wide training for new teaching assistants.

Academic Achievement Award, 2001
Office of International Services, USC

bilal.zafar@ucp.edu.pk
+92-42-35880007 Ext:379
Faculty of Engineering, University of Central Punjab