Sajid Hussain

Sajid Hussain

Sajid Hussain

Assistant Professor

  • Digital Logic Design
  • Computer Organization and Assembly Language
  • Computer Architecture
  • Operating Systems
  • Computer Skills


M.Sc EE (System on Chip)
Linköping University, Linköping, Sweden
Master Thesis:
Verification and FPGA implementation of a floating point SIMD processor for MIMO processing:
Finalized the instruction set simulator of the SIMD processor. Verified the floating point SIMD processor by writing different test vectors in Verilog HDL, this covered the verification of instruction set as well. Wrote assembly code for matrix-inversion algorithm and optimized it for the SIMD processor. Synthesized the SIMD processor to a Virtex-4 FPGA together with a control DSP processor for program download purposes. Finally, performed the post-synthesis netlist simulations to debug the issues where the behavior of the RTL simulation and hardware differs. The debugging was also performed by ChipScope Analyzer.
Bachelor of Computer Engineering
Bahria University, Islamabad, Pakistan


Assistant Professor
University of Central Punjab, Lahore, Pakistan
Teaching courses like Operating Systems, Computer Organization and Assembly Language, Computer Architecture, Digital Logic Design and Computer Skills courses.
Principal Design Engineer
Open-Silicon Pakistan (Pvt.) Ltd, Islamabad, Pakistan
Hybrid Memory Cube Host Controller:
Did design contribution in different modules of HMC especially in the retry mechanism. Developed sequences in UVM for verification of Hybrid Memory Cube host controller IP. Generated coverage reports and analyzed the different modules which did not hit during verification.
Research Assistant
SEECS (NUST), Islamabad, Pakistan
Super speed USB 3.0:
Developed and ran test vectors in Verilog HDL for the verification of both host controller and device side at protocol layer. Bugs were analyzed and fixed after consulting the appropriate designer.
Design Engineer
Palmchip Corporation, Islamabad, Pakistan
SATA Hard Drive:
Extensively verified SATA hard drive controller and its different modules like AES, RDD, Buffer Unit and SATA interface by writing models and test vectors using Verilog HDL. Analyzed bugs, design problems and coverage reports.
Design Engineer
And-Or Logic (Pvt.) Ltd, Islamabad, Pakistan

  • Worked on ARM, MSP and PIC Microcontrollers.
  • Designed more than 9 Multilayer PCBs (got manufactured and tested).


Project Leader
DLL based Frequency Multiplier (VLSI Design)
Designed an Integrated Circuit (IC) in 0.35μm CMOS process using Cadence Tools. Complete project design flow was followed including the architecture analysis, simulation, layout implementation and verification. The area including decoupling capacitors was all fit into a 50 μm x 50 μm space.
Project Member
Audio Control System (Design of Digital Systems)
Designed and Implemented echo control system using VHDL and synthesized on Altera’s DE2 Board using Cyclone II FPGA. The system was also having VGA portion displaying the sound activities. Worked on its VGA portion.
Project Member
Low Power 16×16 Multiplier (Low Power Electronics)
Used different design techniques to achieve low power. The design included Partial Product generators, carry-save adder chain and carry-look-ahead adder.
04235880007 Ext-253
Faculty of Information Technology, University of Central Punjab

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